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| P3C1011 HIGH SPEED 128K x 16 (2 MEG) STATIC CMOS RAM FEATURES High Speed (Equal Access and Cycle Times) -- 10/12/15/20 ns (Commercial) -- 12/15/20 ns (Industrial) -- 20/25/35 (Military) Low Power -- 360 mW (max.) Single 3.3V 0.3V Power Supply 2.0V Data Retention Easy Memory Expansion Using CE and OE Inputs Fully TTL Compatible Inputs and Outputs Advanced CMOS Technology Fast tOE Automatic Power Down when deselected Packages --44-Pin SOJ, TSOP II DESCRIPTION The P3C1011 is a 131,072 words by 16 bits high-speed CMOS static RAM. The CMOS memory requires no clocks or refreshing, and has equal access and cycle times. Inputs are fully TTL-compatible. The RAM operates from a single 3.3V 0.3V tolerance power supply. Access times as fast as 10 nanoseconds permit greatly enhanced system operating speeds. CMOS is utilized to reduce power consumption to a low level. The P3C1011 is a member of a family of PACE RAMTM products offering fast access times. The P3C1011 device provides asynchronous operation with matching access and cycle times. Memory locations are specified on address pins A0 to A17. Reading is accomplished by device selection (CE and output enabling (OE) while write enable (WE) remains HIGH. By presenting the address under these conditions, the data in the addressed memory location is presented on the data input/output pins. The input/output pins stay in the HIGH Z state when either CE or OE is HIGH or WE is LOW. For both reading and writing, the Byte Enable control lines (BLE for I/O0-7 and BHE for I/O8-15) allow for the selection of only 8 of the 16 I/O lines if desired. When a Byte Enable control line is HIGH, the corresponding I/Os are active. Package options for the P3C1011 include 44-pin SOJ and TSOP packages. FUNCTIONAL BLOCK DIAGRAM PIN CONFIGURATION 1519B SOJ TSOP II Document # SRAM131 REV OR Revised March 2006 1 P3C1011 MAXIMUM RATINGS(1) Symbol V CC Parameter Power Supply Pin with Respect to GND Terminal Voltage with Respect to GND Operating Temperature Value -0.5 to +4.6 -0.5 to VCC +0.5 -55 to +125 Unit V Symbol TBIAS TSTG V C IOUT Parameter Temperature Under Bias Storage Temperature DC Output Current Value -55 to +125 -65 to +150 20 Unit C C mA V TERM TA RECOMMENDED OPERATING TEMPERATURE AND SUPPLY VOLTAGE Grade(2) Industrial Commercial Military Ambient Temperature -40C to +85C 0C to +70C -55C to +125C VSS 0V 0V 0V VCC 3.3V 0.3V 3.3V 0.3V 3.3V 0.3V CAPACITANCES(4) VCC = 3.3V, TA = 25C, f = 1.0MHz Symbol CIN COUT Parameter Input Capacitance I/O Capacitance Conditions Typ. Unit VIN = 0V VOUT = 0V 8 8 pF pF DC ELECTRICAL CHARACTERISTICS Over recommended operating temperature and supply voltage(2) Symbol VIH VIL VOL VOH Parameter Input High Voltage Input Low Voltage Output Low Voltage (TTL Load) Output High Voltage (TTL Load) Input Leakage Current IOL = +8 mA, VCC = Min. IOH = -4 mA, VCC = Min. VCC = Max. VIN = GND to VCC VCC = Max., ILO Output Leakage Current CE = VIH, VOUT = GND to VCC CE VIH ISB Standby Power Supply VCC= Max, Current (TTL Input Levels) f = Max., Outputs Open VIN VIH or VIN VIL CE VCC - 0.2V ISB1 Standby Power Supply Current (CMOS Input Levels) VCC= Max, f = 0, Outputs Open VIN VCC - 0.3V or VIN 0.3V ___ 10 mA ___ 40 mA -1 +1 A 2.4 -1 +1 Test Conditions P3C1011 Unit Min Max VCC +0.3 V 2.0 -0.3(3) 0.8 0.4 V V V A ILI Document # SRAM131 REV OR Page 2 of 10 P3C1011 POWER DISSIPATION CHARACTERISTICS VS. SPEED Symbol Parameter Temperature Range Commercial -10 90 N/A N/A -12 85 95 N/A -15 80 90 N/A -20 75 85 100 -25 70 80 95 -35 65 75 90 Unit mA mA mA ICC Dynamic Operating Current* Industrial Military *VCC = 3.6V. Tested with outputs open. f = Max. Switching inputs are 0V and 3V. CE = VIL, OE = VIH. AC ELECTRICAL CHARACTERISTICS--READ CYCLE (VCC = 3.3V 0.3V, All Temperature Ranges)(2) Sym. t RC tAA tAC t OH tLZ t HZ tOE Parameter Read Cycle Time Address Access Time Chip Enable Access Time Output Hold from Address Change Chip Enable to Output in Low Z Chip Disable to Output in High Z Output Enable Low to Data Valid 3 3 -10 10 10 10 3 3 5 5 12 -12 15 12 12 3 3 6 6 -15 20 15 15 3 3 7 7 -20 -25 -35 Unit ns 35 35 ns ns ns ns 12 12 ns ns Min Max Min Max Min Max Min Max Min Max Min Max 25 20 20 3 3 8 8 10 10 25 25 35 3 3 tOLZ t OHZ tPU tPD tBE tLZBE tHZBE Output Enable Low to Low Z Output Enable High to High Z Chip Enable to Power Up Time Chip Disable to Power Down Time Byte Enable to Data Valid Byte Enable to Low Z Byte Disable to High Z 0 5 0 10 5 0 6 0 6 0 12 6 0 6 0 7 0 15 7 0 7 0 8 0 20 8 0 8 0 10 0 25 10 0 10 0 12 0 35 12 0 12 ns ns ns ns ns ns ns Document # SRAM131 REV OR Page 3 of 10 P3C1011 TIMING WAVEFORM OF READ CYCLE NO. 1 TIMING WAVEFORM OF READ CYCLE NO. 2 (OE CONTROLLED)(5,6) OE Notes: 1. Stresses greater than those listed under MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to MAXIMUM rating conditions for extended periods may affect reliability. 2. Extended temperature operation guaranteed with 400 linear feet per minute of air flow. 3. Transient inputs with VIL not more negative than -2.0V and VIH VCC + 0.5V, are permissible for pulse widths up to 20 ns. 4. This parameter is sampled and not 100% tested. 5. WE is HIGH for READ cycle. 6. CE is LOW and OE is LOW for READ cycle. 7. ADDRESS must be valid prior to, or coincident with CE transition LOW. 8. Transition is measured 200 mV from steady state voltage prior to change, with loading as specified in Figure 1. This parameter is sampled and not 100% tested. 9. Read Cycle Time is measured from the last valid address to the first transitioning address. Document # SRAM131 REV OR Page 4 of 10 P3C1011 AC CHARACTERISTICS--WRITE CYCLE (VCC = 3.3V 0.3V, All Temperature Ranges)(2) Sym. tWC tCW Parameter Write Cycle Time Chip Enable Time to End of Write Address Valid to End of Write Address Set-up Time to Write Start Write Pulse Width Address Hold Time Data Valid to End of Write Data Hold Time Write Enable to Output in High Z Output Active from End of Write WE High to Low Z Byte Enable to End of Write -10 10 7 12 8 -12 15 10 -15 20 10 -20 25 12 -25 35 15 -35 Min Max Min Max Min Max Min Max Min Max Min Max Unit ns ns tAW tAS tWP tAH tDW t DH tWZ tOW tLZWE tBW 7 0 7 0 5 0 5 3 3 7 8 0 8 0 6 0 6 3 3 8 10 0 10 0 7 0 7 3 3 10 10 0 10 0 8 0 8 3 3 10 12 0 12 0 10 0 10 3 3 12 15 0 15 0 12 0 12 3 3 15 ns ns ns ns ns ns ns ns ns ns TIMING WAVEFORM OF WRITE CYCLE NO. 1 (CE CONTROLLED) CE Document # SRAM131 REV OR Page 5 of 10 P3C1011 TIMING WAVEFORM OF WRITE CYCLE NO. 2 (BLE OR BHE CONTROLLED) BLE TIMING WAVEFORM OF WRITE CYCLE NO. 3 (WE CONTROLLED, OE LOW) WE Document # SRAM131 REV OR Page 6 of 10 P3C1011 AC TEST CONDITIONS Input Pulse Levels Input Rise and Fall Times Input Timing Reference Level Output Timing Reference Level Output Load VSS to 3.0V 3ns 1.5V 1.5V See Figures 1 and 2 Figure 1. Output Load * including scope and test fixture. Note: Because of the ultra-high speed of the P3C1041, care must be taken when testing this device; an inadequate setup can cause a normal functioning part to be rejected as faulty. Long high-inductance leads that cause supply bounce must be avoided by bringing the VCC and ground planes directly up to the contactor fingers. A 0.01 F high frequency capacitor is also required between VCC and ground. To avoid Figure 2. Thevenin Equivalent signal reflections, proper termination must be used; for example, a 50 test environment should be terminated into a 50 load with 1.73V (Thevenin Voltage) at the comparator input, and a 116 resistor must be used in series with DOUT to match 166 (Thevenin Resistance). TRUTH TABLE Mode Power-down Read All Bits Read Lower Bits Only Read Upper Bits Only Write All Bits Write Lower Bits Only Write Upper Bits Only Selected, Outputs Disabled CE H L L L L L L L O E W E BLE BHE X L L L X X X H X H H H L L L H X L L H L L H X X L H L L H L X I/O0 - I/O7 High Z DOUT DOUT High Z DIN DIN High Z High Z I/O8 - I/O15 High Z DOUT High Z DOUT DIN High Z DIN High Z Power Standby Active Active Active Active Active Active Active Document # SRAM131 REV OR Page 7 of 10 P3C1011 ORDERING INFORMATION Document # SRAM131 REV OR Page 8 of 10 P3C1011 Pkg # # Pins Symbol A A1 b C D e E E1 E2 Q J8 44 (400 mil) Min Max 0.128 0.148 0.082 0.013 0.023 0.007 0.013 1.120 1.130 0.050 BSC 0.435 0.445 0.395 0.405 0.370 BSC 0.025 - SOJ SMALL OUTLINE IC PACKAGE Pkg # # Pins Symbol A A2 b D E e HD T2 44 Min Max 0.039 0.047 0.033 0.045 0.012 0.016 0.396 0.404 0.721 0.729 0.0315 BSC 0.462 0.470 TSOP II THIN SMALL OUTLINE PACKAGE Document # SRAM131 REV OR Page 9 of 10 P3C1011 REVISIONS DOCUMENT NUMBER: DOCUMENT TITLE: REV. OR ISSUE DATE Mar-06 SRAM131 P3C1011 HIGH SPEED 128K x 16 (4 MEG) STATIC CMOS RAM ORIG. OF CHANGE JDB DESCRIPTION OF CHANGE New Data Sheet Document # SRAM131 REV OR Page 10 of 10 |
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